Scaling down of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) is an important trend of the developing for integrated circuit technology, in order to improve integration level and reduce manufacturing cost. However, as is known to those skilled in the art, scaling down of the MOSFET will cause short channel effect. As the scaling down of the MOSFET, an effective length of a gate reduces accordingly. As a result, a proportion of depletion layer charges controlled by a gate voltage decreases, causing a threshold voltage decreases as a channel length decreases.
In the MOSFET, it is desirable to increase the threshold voltage of the device to suppress the short channel effect. On the other hand, in applications with low-voltage supply or applications employing both p-type MOSFETs and n-type MOSFETs, for example, it is also desirable to lower down the threshold voltage of the device to reduce power consumption.
Channel doping is a known method for adjusting the threshold voltage. However, if a dopant density of a channel region is increased to enhance the threshold voltage of the device, carrier mobilities will decrease, causing degradation of device performance. Furthermore, high-density ions in the channel region may neutralize ions in portions of source/drain regions adjoining the channel region. As a result, ion density in these portions decreases, causing device resistance to increase.
Yan et al. proposed in “Scaling the Si MOSFET: From bulk to SOI to bulk,” IEEE Trans. Elect. Dev. Vol. 39, p. 1704, July, 1992, that in an SOI (Semiconductor-on-Insulator)-type MOSFET, a ground plane (i.e., a grounded backgate) can be disposed under a buried insulation layer to suppress the short channel effect.
In case that a plurality of MOSFETs are integrated on a wafer, backgates being biased with different electrical fields can be disposed under respective buried insulation layers of the plurality of MOSFETs to adjust the threshold voltages of the respective MOSFETs. However, with the scaling down of the device continuously, reliable electrical insulation between the backgates of adjacent MOSFET devices has become an urgent problem to be solved. Moreover, it also becomes difficult to achieve reliable electrical insulation between conductive vias of adjacent MOSFET devices.